1. Technical Field
The present disclosure relates to switching mode power supplies and in particular to pulse width modulation regulation devices (PWM) used in these power supplies.
2. Description of the Related Art
FIG. 1 schematically shows a conventional switching mode power supply. The regulated voltage Vout is taken from the terminals of a filtering capacitor Cf. This capacitor is connected in series with an inductor L between a reference potential, the ground Vground, and the output of a push-pull stage 10 formed by a pair of complementary MOS transistors, powered between the ground and a positive voltage Vbattery, for example a battery voltage.
A differential amplifier 12 supplies an error voltage Verror proportional to the difference between a reference voltage Vreference and the output voltage Vout. A comparator 14 receives the voltage Verror and a periodic sawtooth signal Vper produced by a ramp generator 16. The comparator 14 thus supplies a pulse width modulated signal whose duty factor is proportional to the error voltage Verror. This pulse width modulated signal is shaped by a circuit DRV driving the complementary pair 10.
FIG. 2 is a chronogram showing the generation of the pulse width modulated signal from the error signal Verror and the sawtooth signal Vper. The signal comprises Vper a periodic succession of rising ramps of same slope, starting from 0 and whose magnitude is constant and lower than Vbattery.
In FIG. 2, the voltage Verror is halfway up the ramps and defines a pulse width modulation signal having a duty factor of 0.5—the pulse width modulated signal is at 1 for the part of the ramps below Verror, and at 0 for the part of the ramps above Verror.
Details about making and operating systems of this type are described in [<<Fundamentals of Power Electronics>>, Robert W. Erikson, Dragan Maksimovic; Kluwer Academic Publishers; 3rd Revised edition (January 2001)].
In FIG. 2, when the error voltage Verror tends toward 0, i.e., when the output current of the switching mode power supply is low, the duty factor of the pulse width modulated signal also tends toward 0. Given the reaction time of the circuits, it is not possible to generate pulses having a quasi-zero width, hence it results that the duty factor becomes inaccurate. This inaccuracy is increased by the fact that the signal Verror, tending toward 0, disappears in the noise and its fluctuations become indistinguishable by the comparator 14. The result is fluctuations of the regulated voltage Vout when it tends toward its setpoint value, which may be unacceptable in some applications.
To avoid this drawback, it has been suggested to connect the low power supply terminal of the comparator to a negative power supply source with respect to the Vground, so that the comparator may take a low noise measurement of the voltage Verror when it tends toward 0. It therefore uses an additional power supply source.
It has also been suggested to set a reduced value of the duty factor, so that the pulse width always remains in a range where it may be determined with enough accuracy. It renders the system more complex due to the fact that this offset must be compensated when the output voltage is near the setpoint voltage. In addition, because the system is then always in a switching mode, especially when idle, the current consumption is increased.